One type of deposition apparatus used in the semiconductor industry is a single wafer chamber apparatus in which one wafer at a time is placed in the deposition chamber and a layer of a material is deposited on the wafer. Referring to FIG. 1, there is shown one form of a typical single wafer deposition apparatus 10. Deposition apparatus 10 comprises an enclosed chamber 12 formed by an upper dome 14, a lower dome 16 and a side wall 18 between the upper and lower domes 14 and 16. A flat susceptor 20 is mounted in and extends across the chamber 12. The susceptor is generally mounted on a shaft 22 which provides for rotation of the susceptor 20. A pre-heat ring 21 is around the periphery of the susceptor 20 and extends between the susceptor 20 and the side wall 18. A deposition gas inlet port 24 extends through the side wall 18 of the chamber 12. An exhaust port 26 also extends through the side wall 18 of the chamber 12. An exhaust port 26 also extends through the side wall 18 substantially diagonally opposite the inlet port 24. Heating means, such as lamps 28, are mounted around the chamber 12 and direct their light through the upper and lower domes 14 and 16 onto the susceptor 20 and pre-heat ring 21 to heat the susceptor 20 and the pre-heat ring 21. A door, not shown, is also provided in the side wall 18 through which wafers can be inserted into and removed from the chamber 12.
To deposit a layer of a material, such as silicon, on the surface of a wafer 30, the wafer 30 is placed on the susceptor 20 and a flow of a deposition gas is provided across the chamber 12 from the inlet port 24 to the exhaust port 26. To deposit silicon, the gas used contains a silicon containing material, such as silane, and an inert carrier gas, such as hydrogen. The susceptor 20 and wafer 30 are heated by the lamps 28. The heated susceptor 20, pre-heat ring 21 and wafer 30 heat the deposition gas passing over their surfaces causing the gas to react and deposit a layer of the material, silicon, on the surface of the wafer 30.
The heat from the lamps 28 is absorbed by the susceptor 20 and is normally transferred to the wafer 30 by conduction across a thin interface between the wafer 30 and the susceptor 20. The wafer 30 and susceptor 20 are in fairly intimate contact with the wafer 30 being mounted on the susceptor 20. However, as shown in FIG. 2, the surface of the susceptor 20 is not perfectly smooth, but has some roughness. Because of the surface roughness of the susceptor 20, the wafer 30 actually only contacts the surface of the susceptor 20 at a few points. The flatness of the wafer 30 and the susceptor 20 are within a few thousandths of an inch so that the heat is readily conductive through the gas molecules that occupy the space between the wafer 30 and the susceptor 20. As shown in FIG. 3, in some cases, the surface of the susceptor 20 is curved or recessed away from the wafer 30 (typically 2 to 10 thousands of an inch) to avoid hot spots resulting from the point contact of the wafer and susceptor. However, in either case, the primary heat transfer between the wafer 30 and susceptor 20 is conduction across the gas film between the two surfaces. Radiation heat transfer does occur, but is of secondary importance because of the close spacing of the wafer 30 to the susceptor 20.
During the process of depositing a layer of a material, such as silicon, on the surface of the wafer 30, molecules containing the material, typically silane for silicon, diffuse to the back surface of the wafer 30. This results from the fact that the molecules are driven by a partial pressure difference since there are initially no such molecules between the wafer 30 and the susceptor 20. These atoms thermally decompose and deposit silicon on the back surface of the wafer 30 and the corresponding surface of the susceptor 20. However, this deposition is typically confined to a few millimeters from the edge of the wafer 30. For the manufacture of certain types of semiconductor devices, such as integrated circuits, it is sometimes desirable to deposit silicon on the entire back surface of the wafer 30 as well as on the front surface of the wafer 30. Although uniformity of the layer deposited on the back surface of the wafer 30 is not an issue, it is important to have complete coverage. Also, for time saving, it would be desirable to be able to coat the back surface of the wafer 30 at the same time that the coating is being applied to the front surface of the wafer 30.
As one example of the need for complete coverage of a coated wafer in a cold wall CVD process where the wafer is being prepared for certain applications, FIG. 7 demonstrates a wafer 70 in which incomplete coverage of the underside has taken place. As shown, a polysilicon layer 71 is deposited on a silicon wafer substrate 72. In most applications the wafer substrate will generally have a thin coating of silicon dioxide (SiO.sub.2) 73 which acts as an interface layer for the overcoated polysilicon layer 71.
When a polysilicon coating 71 is applied by means of a cold wall CVD apparatus as shown in FIG. 1, the coverage on the wafer is incomplete, generally coating the outer periphery of the underside of the wafer to a distance of 1/4 inches to 3/4 inches from the wafer's edge of the wafer. This leaves a significant portion 76 of the underside oxide interface coating exposed which increases the risks of a defective wafer in certain applications. For example, certain wafer uses require a hydrofluoric acid (HF) dip as a step after the chemical vapor deposition of the polysilicon. In such a step the HF will etch the exposed underside portion 76 of the silicon dioxide layer 73. This erosion will cause a gap 75 between the polysilicon 71 and the underside oxide. Such loose ends of the polysilicon as shown in FIG. 7 will enevitably generate flakes of loose polysilicon particles. These particulate flakes become contaminants to the HF bath and the wafer itself becomes a source of potential contamination in any subsequent fabrication processing of the wafer. This example amply demonstrates the need for a device and process for securing total coverage of a wafer substrate in a cold wall/heated susceptor application.